1. Field of the Invention
The present invention relates to a semiconductor memory device and its fabricating method and more particularly, to a capacitor structure and a storage node electrode structure in a DRAM.
2. Description of the Related Art
Recently, MOS type DRAM technology has made remarkable progress in providing high integration and large capacity of memory cells with the advancement of semiconductor techniques, particularly fine processing techniques.
However, the high memory integration presents a problem in that the area of a capacitor for storing data (charges) is decreased and this results in erroneous reading operation of the memory contents or in the generation of a soft error caused by the destruction of the memory contents due to .alpha. rays or the like. Further, the high integration and large capacity have led to another problem that the gate length of a transistor is shortened and thus the reliability is lowered.
For the purpose of solving such problems and realizing the higher integration and increased capacity, there have been suggested various methods of forming on a silicone substrate, storage nodes made of polycrystalline silicon or the like so as to enlarge an area for the capacitors, thus increasing the capacitance of the capacitors.
Further, a laminated memory cell structure has been proposed, in which a MOS capacitor is formed on a memory cell zone and one electrode of the capacitor is electrically connected to one electrode of a switching transistor formed on a semiconductor substrate to thereby substantially increase the electrostatic capacitance of the MOS capacitor.
Such laminated memory cell is shown in FIG. 15. In more detail, one memory cell area is provided by isolating a p-type silicone substrate 101 with an insulating film 102. In the memory cell area, a gate electrode 106 is formed between adjacent source/drain regions 104 of an n-type diffusion layer with a gate insulating film 105 disposed between the gate electrode 106 and source/drain regions 104, thereby forming a MOSFET as a switching transistor. Further formed on the MOSFET is a first capacitor electrode 110. The first capacitor electrode 110 is contacted through its storage node contact hole 108 provided in an insulating film 107 with one of the source/drain regions of the MOSFET, and covers the gate electrode 106 of the MOSFET and a gate electrode (word line) of an adjacent MOSFET. An insulating film 111 and a second capacitor electrode 112 are sequentially laminated on the first capacitor electrode 110 to thereby form a capacitor. Reference numerals 107' and 107" denote inter-layer insulating films, 113 a bit line contact hole and 114 a bit line.
The laminated memory cell is fabricated in the following manner.
First, in a memory cell zone defined by the insulating film 102 formed in the p-type silicone substrate 101, a gate electrode is formed on the substrate by the gate insulating film 105, and then source/drain regions 104a and 104b in the form of an n-type diffusion layer are formed. Thus, a MOSFET as a switching transistor is formed.
Then, the insulating film 107 made of an silicon oxide is formed on the MOSFET. In the insulating film 107, a storage node contact hole 108 for contact with the source drain region 104b is formed. Then a pattern of first capacitor electrode 110 made of a heavily doped polycrystalline silicon film is formed.
Subsequently, on the first capacitor electrode 110, a capacitor insulating film 111 of silicon oxide and a polycrystalline silicon film are sequentially deposited.
Finally, the polycrystalline silicon film is subjected to a doping process and then to photolithographic and reactive ion etching processes to obtain a pattern of second capacitor plate electrode 112. At this stage, a MOS capacitor is formed and the basic structure of a cell part is completed.
With such a structure, the storage node electrode can be extended up to a position above the element isolation zone and the step difference of the storage electrode can be utilized, whereby the capacitance of the capacitor can be increased several to several tens of times than that of a planar structure type.
A DRAM of such a laminated memory cell structure type, however, has the following disadvantage. As the memory integration is advanced and each element is correspondingly made smaller, the area for the memory cells is reduced and the area of the flat part of the storage node electrode is reduced, thus making it more difficult to produce a capacitor having a large capacitance.
To eliminate the disadvantages, it is proposed to make the storage node electrode thicker to increase the area of its side part. This proposal however, presents the problem that, as the thickness of the storage node electrode is increased, the step difference of the storage electrode is increased. Thus, it becomes difficult to carry out the subsequent processes, in particular, the etching process.
In order to avoid this problem, it has been suggested that the storage node electrode should be made in the form of a multi-layer fin as schematically shown in FIG. 16.
This structure is effective to increase the capacitor area. However as the cell becomes smaller, its effectiveness decreases. The reason is as follows. As the cell becomes smaller the ratio of the side wall part area to the entire storage electrode area is increased. Accordingly, in the storage node electrode of a fin structure, the area of the side walls becomes smaller than that of a storage node electrode of a single-layer structure having the same height.
As seen from the foregoing, even in the DRAM of the improved laminated memory cell structure, as the cells become smaller due to the high integration of a device, the memory-cell area and the area of flat part of the storage node electrode are decreased. Therefore, it is very difficult to form a capacitor having a sufficient capacitance.